Keyword Search (Enter Skills, Location, etc.)

Digital Design Engineer, VHDL, Low Power Design, RTL, Communication Protocols, 3+ years, Multi-billion German MNC, Bangalore

Company: Multi-billion German MNC 
is a multinational engineering and electronics company headquartered in Germany. It is one of the world's leading global supplier of technology and services, offering end to end engineering, IT and Business solutions to automotive, industrial products (including drives and controls, packaging technology and solar panels) and consumer goods and building products (including household appliances, power tools, security systems and thermotechnology.
The company works on exciting technologies ranging from AUTOSAR initiatives to embedded systems, automotive technologies to multimedia technologies, security systems to industrial systems, and many more.
The company was founded in 1886 and has some 3,00,000+  employees worldwide. It has more than 350 subsidiaries across over 60 countries and its products are sold in around 150 countries. In 2010 it invested around €3.8 billion in research and development and applied for over 3,800 patents worldwide. In 2009 the company was the leader in terms of numbers of patents at the German Patent and Trade Mark Office (GPTO) with 3,213 patents.
(source: wikipedia and company website)

Senior Digital Design Engineer

The job includes design and characterization of digital IPs. The typical IPs could be the communication protocol IPs(e.g SPI, CAN, PSI) and other logic in ASIC SOC design(clock generators, reset etc). As an individual contributor, the person will be responsible for architecture, design, verification, delivery of test patterns to tester team, post silicon characterization/validation. The candidate is expected to understand the layout issues .


·         B-Tech/BS with Minimum 5 yrs or MTech/MS with Minimum 3 Years of relevant Digital Design Experience.

 Skill set:

·         In Depth Knowledge of VHDL Based IC Design and Synthesis.
·         Experience in Low Power Design Techniques.
·         Experience in RTL design of communication protocols IPs(eg SPI, CAN )
·         Experience in Clock Domain Crossing Verification.
·         Excellent communication skills,
·         Willingness to Take Ownership and Responsibility and Learn New Tasks. 


·         Design Compiler
·         Cadence/Synopsys/Mentor Graphics tools for simulation(Incisive/VCS/Questa)
·         CDC tools(Mentor, Cadence)

Work location: Bangalore

Interview location: Bangalore; must be available for personal interview on short notice.

Apply to  with subject line "RB-DIGI-DES